Etching of openings for forming electrical interconnects in the semiconductor processing industry is becoming more demanding as device sizes shrink. For example, as device sizes shrink to 0.15 microns and lower, the profiles of electrical contact holes can affect increasingly stringent electrical operating design requirements of integrated circuits.
There are a wide variety of variables that affect the anisotropicity of etching profiles in etching contact openings with an aspect ratio from about 3 to about 6. For example as the aspect ratio increases, the phenomenon of etch stop may occur where there is a build-up of fluoropolymers created during the plasma etching process along the sidewalls in the bottom of the etched opening which can degrade anisotropicity, effectively resulting in a cessation of anisotropic etching and the degradation of etching profiles. A degradation of etching profiles where the upper portion of the contact opening has a larger diameter may adversely affect both electrical resistance and capacitance of the integrated circuit.
While the formation of semiconductor devices of the prior art where device sizes have been relatively larger with a wider window for electrical property variations have had correspondingly greater room for variation in etching profiles and a greater tolerance for non-selective etching processes, increasingly stringent design requirements require an increasingly greater level of accuracy in forming electrical contacts.
For example, in ultra low power devices, for example a static random access memory device (SRAM), which require periodic refresh signals to retain stored data, the ratio of standby current (Isb) to drive current (Idr) is a critical design parameter in low power devices to enable proper functioning. For example, in creating an SRAM device it is frequently desirable to have an etch stop layer in an reactive ion etching (RIE) process to form contact openings since the relative depth of different contact openings in an etching process may vary, requiring an effective etch stop layer to prevent premature etch through.
One problem according to prior art RIE etching processes deals with the sufficient selectivity of etch stop layers. For example, forming contact openings including sufficient etch stop layer etching resistance to prevent premature etch-through while maintaining sufficient etching selectivity in a subsequent etching process to avoid contact opening enlargement at an upper portion of the contact opening is difficult to achieve according to the design requirements required, for example for 0.15 micron low power SRAM devices.
There is therefore a need in the semiconductor manufacturing art for an improved method to form sub-micron semiconductor devices including an anisotropic etching process such that anisotropically etch contact openings are formed with improved etching profiles to satisfy electrical design constraints.
It is therefore an object of the invention to provide an improved method to form sub-micron semiconductor devices including an anisotropic etching process such that anisotropically etch contact openings are formed with improved etching profiles to satisfy electrical design constraints as well as overcoming other shortcomings in the prior art.